1. Field of the Invention
The present invention relates to wafer-scale integrated circuit memories.
2. Description of the Prior Art
A wafer scale integrated circuit is an integrated circuit which covers the entire area of a semiconducting wafer. The wafer is usually circular and is several inches in diameter. The circuit comprises one or more data ports whereby digital data and instructions can be passed into and/or out of the wafer. The circuit also generally comprises a plurality of data processing cells. The failure rate in circuit fabrications means that not all of the cells are necessarily functional. The cells are therefore testable. Starting at a port, a cell adjacently contiguous to that port is tested. If it passed the test it is coupled to the port for data transfer and can be used for data processing. If it does not pass the test another adjacently contiguous cell is chosen and tested. A cell which has passed the test can then behave as the port and test another adjacently contiguous cell. The end result of the testing routine is a chain or chains of tested, working cells starting at the port. Various forms for the chain are known in the art and others have been proposed. The exact form of chain connection is not part of the present invention.
It is known to use such wafer scale integrated circuit as a memory. The manner of memory storage can be in a continuous shift register loop starting and finishing at the the port. The data moves steadily between an input and an output terminal in the port. Individual data storage shift registers in the cells can be connected in series to provide a long, slow, data storage loop. Other shift registers of a much shorter length can be connected in parallel with the slow loop to form one or more fast, data access and/or data depositing lines. Data can be transferred between the fast and slow lines at a plurality of nodes, at least one in each cell. In this form of memory it is difficult to keep track of the position in the slow loop of any particular package of data. Complicated controllers are required to determine the node from which a data package can be recovered or inserted into the slow line. The control of the transfer requires additional control shift registers in parallel with the slow, data storage shift register chain.
The manner of data storage in such a memory can also be in a selectable storage shift register in a selectable cell, such shift registers not being connected in series. A data input line winds between the cells. This line carries an instruction or instructions destined for a specific cell. When the instruction reaches the cell, the cell responds by storing the data following the instruction or by retrieving data and returning it to the port via a data reply line which also winds among the cells. In such a memory it is also necessary to provide a controller for deciding where a particular piece of data is to be stored and for providing the instruction to retrieve a piece of data when that data is called for.
In general keeping track of data is a costly business requiring controllers, data processing software packages and the like. In addition, such memories may employ destructive readout whereby data is physically removed from its place or storage and required to be replaced if readout is not to be destructive.
It is therefore desirable to provide a wafer-scale integrated circuit memory wherein it is not necessary to provide separate means for keeping track of the location of stored data and wherein data recovery can be achieved in a non-destructive manner.